On September 30, 2026, Google announced Gemini 4 Argon, the first model of the Gemini 4 generation.
Two things got attention. It can output up to 1 million tokens in one go (up from 64,000), and its security capabilities are strong enough that Google is giving it to cyber defense organizations before the general public.
This post does not dwell on benchmarks. Following our look at the Texas data center behind GPT-6 Astra, it looks at what sits underneath this model.
The short version: Google starts from a different place than OpenAI. OpenAI rented someone else’s GPUs in someone else’s building. Google builds the chips, the network, the buildings and the software itself.
First: what Google disclosed and what it didn’t
This matters most. Argon’s training infrastructure has not been officially disclosed.
I read Google’s announcement post and the separate evaluation document (Model evaluation) published by DeepMind. There is no chip name, no chip count and no training duration. There is no official model card yet either.
| Category | Details |
|---|---|
| Disclosed | 1M-token output limit, pricing, benchmarks, internal Google use cases, Fairwind-first rollout |
| Not disclosed | Training chip generation, chip count, training duration, parameter count, training data cutoff |
A few model-info sites state that “Argon runs on sixth-generation TPUs (Trillium).” I could not find support for that in any first-party Google source. This post does not use that claim.
So what this post does is narrow the range, not guess. Using the chip specs and timelines Google has published, plus the money flow, it draws an outline of what must be true at minimum.
① The starting point: renting GPUs vs. making chips
The training setup for the Gemini family has been the same every time. Earlier model cards state that the models were trained on Google’s TPUs using JAX and ML Pathways.
Some terms first.
- TPU (Tensor Processing Unit): a chip Google designed purely for AI computation. It plays the same role as an Nvidia GPU, but it could not be bought outside Google — you could only rent it on Google Cloud.
- JAX: Google’s machine learning framework, filling the same role as PyTorch.
- Pathways: Google’s distributed runtime that lets a single Python process direct thousands to tens of thousands of chips.
Why this combination matters becomes obvious next to the Astra post.
| OpenAI (GPT-6 Astra) | Google (Gemini 4 Argon) | |
|---|---|---|
| Chips | Nvidia B200 and B300 (purchased) | TPU (designed in-house) |
| Building | Stargate, owned by Oracle (leased) | Google’s own data centers |
| Chip-to-chip network | Nvidia NVLink + third-party gear | Google’s own ICI and optical switches |
| Training software | In-house stack | JAX + Pathways (in-house) |
| Training infra disclosed | “Over 100,000 GPUs” remark | Not disclosed |
Google fills every cell in the right-hand column by itself. That is vertical integration. It means the chip designers sit next to the model researchers. Google said as much when it introduced its seventh-generation TPU: “DeepMind researchers and TPU engineers designed it together.”
② Training candidates: Ironwood and TPU 8t
So which generation was Argon trained on? Two recent generations are plausible candidates.
| 7th-gen Ironwood | 8th-gen TPU 8t | |
|---|---|---|
| Announced | April 2025 | April 22, 2026 |
| General availability | Announced November 2025 | Planned for second half of 2026 |
| Compute per chip | 4,614 TFLOPS (FP8) | 12.6 PFLOPS (FP4) |
| Memory per chip (HBM) | 192 GB | 216 GB |
| Memory bandwidth | 7.37 TB/s | 6.5 TB/s |
| One unit (superpod) | 9,216 chips | 9,600 chips |
| Superpod compute | 42.5 exaflops | 121 exaflops |
| Performance per watt | — | Up to 2x Ironwood |
Two notes on reading this table.
First, do not compare the compute numbers directly. Ironwood is quoted in FP8 and 8t in FP4. FP8 and FP4 describe how many bits are used to represent one number. Fewer bits mean faster math but less precision. The same chip roughly doubles its number when counted in FP4. Google itself describes the generational gap as “nearly 3x the compute per pod.”
Second, a superpod is about 9,000 chips tied together to act as one. Google builds it with dedicated chip-to-chip links (ICI, Inter-Chip Interconnect) and optical circuit switches (OCS) that rewire the connection shape with light. A failed block of chips can be swapped out for another within about ten seconds.
Narrowing it down by timeline
Lined up by date:
Apr 2025 Ironwood announced
Nov 2025 Ironwood general availability
Apr 2026 TPU 8t and 8i announced (Cloud Next)
Q3 2026 TPU 8 early access begins
Sep 2026 ← Gemini 4 Argon announced
H2 2026 TPU 8 general availability planned
Pretraining a frontier model (teaching it from scratch on a huge dataset) usually takes months, followed by several more months of post-training and safety evaluation.
Seen that way, it seems unlikely that a model released in September was pretrained from start to finish on a chip announced in April. That would change if Google had deployed 8t internally well before the public announcement, but no such disclosure exists.
The least strained reading is “Ironwood was the main workhorse, possibly with some eighth-generation hardware mixed in.” But that is an inference from the timeline, not a fact. Until Google says otherwise, that is as far as one can go.
The upper bound on scale
One number Google published alongside the 8t announcement is worth remembering.
A single block of the new Virgo data center network can tie together more than 134,000 TPU 8t chips, and with JAX and Pathways, over 1 million chips can be used as a single training cluster.
OpenAI said in September that running “over 100,000 GPUs at once was a first.” Google talks about 134,000 chips on one network and 1 million in software as its ceiling. We don’t know how many Argon actually used. But the scale Google designs for is an order of magnitude above what OpenAI has just reached.
③ A million output tokens is an infrastructure problem
Argon’s headline number is 1 million output tokens. That is about 15x the previous Gemini’s 64,000 tokens and about 8x Astra’s 128,000.
Why this is an infrastructure story takes some explaining.
When an AI writes, it produces one token at a time, in order. This stage is called decoding. And every time it produces the next token, it has to refer back to everything written so far.
Recomputing from scratch each time would be far too slow, so the intermediate results are kept in memory. This is called the KV cache.
The problem is that this cache keeps growing as the output gets longer. Over 1 million tokens the cache swells without end, and for every single token the chip has to read that enormous cache from memory.
So the bottleneck for long outputs is not compute speed. It is memory capacity and memory read speed, and, when the cache is spread across many chips, the time chips spend exchanging data.
What the eighth-generation inference chip targets
This is why Google split the eighth generation into a training chip (8t) and an inference chip (8i) in April. The 8i design is aimed almost entirely at this one problem.
| TPU 8i design | Number | Problem it targets |
|---|---|---|
| Memory per chip (HBM) | 288 GB | Room for a growing KV cache |
| Memory bandwidth | 8.6 TB/s (about 1.3x the 8t) | Reading the cache for every token |
| On-chip SRAM | 384 MB (3x the previous generation) | Keeping hot cache right next to the chip |
| Max distance between chips | 7 hops (16 in the old topology) | Time to gather a scattered cache |
| Dedicated aggregation engine (CAE) | One-fifth the aggregation latency | Time to combine results across chips |
SRAM is very fast but small memory built into the chip. HBM is large memory stacked beside the chip. Think of them as a desk (SRAM) and a bookshelf (HBM): the bigger the desk, the fewer trips to the shelf.
A hop is a chip that data passes through on the way to its destination. Earlier TPUs were wired as a cube-shaped grid (3D torus), where the two farthest chips among 1,024 were 16 hops apart. The 8i cuts that to 7 hops with Boardfly, a topology that groups chips by board and jumps between groups through optical switches.
Google describes the 8i as built for long chain-of-thought and low-latency inference of MoE models. That is exactly what Argon is. However, there has been no announcement that Argon is currently served on 8i. The 8i itself is not yet generally available.
Traces left in the price
Argon’s standard price is $4 per million input tokens and $20 per million output tokens. The launch price is half that ($2/$10).
According to reports citing the independent evaluator Artificial Analysis, it matches GPT-6 Astra’s overall score at about 60% of the cost.
A company that makes its own chips does not pay Nvidia a margin. That alone cannot be called the whole explanation for the price gap (model size, launch discounts and market-share strategy are all mixed in). But having structural room to sell the same performance for less is the most direct effect of vertical integration.
④ The model fixed its own data centers
From an infrastructure point of view, the most interesting part of the announcement was elsewhere.
Argon agents analyzed fleet-wide profiling data across Google’s data centers and autonomously found and applied memory optimizations. Once rolled out, these free up more than 300 TiB of memory, with total savings estimated at 500 TiB to 1 PiB.
Profiling means recording where a program spends time and memory while it runs. Google collects this continuously across its entire data center fleet.
How big is 300 TiB? In servers with 128 GB of memory each, it is about 2,400 servers’ worth. 1 PiB is more than three times that. It means getting that much memory back just by changing code, without buying a single new server.
The same announcement had similar examples.
- In Google’s open-source video decoder libgav1, 32,000 lines of SIMD code were rewritten, making it 2.7x faster with identical video output.
- It has been put to work migrating C/C++ code to Rust across Google, including pieces over 800,000 lines long such as the kernel (Zircon) of the Fuchsia operating system.
The point for cloud engineers is this: infrastructure efficiency work is starting to become the model’s job instead of a person’s. Reading profile data, finding the cause, fixing it and measuring again — that has been the work of performance engineers until now.
⑤ The money underneath
The number holding all this up is capital spending.
| Item | Number |
|---|---|
| Alphabet 2026 capex outlook | $195–205 billion (raised from $180–190 billion) |
| Q2 2026 capex | $44.9 billion (about double the same quarter a year earlier) |
| Q2 free cash flow | –$5.9 billion — the first negative quarter since the 2004 IPO |
| Spending mix | About 60% servers, 40% data centers and networking |
Alphabet has signaled that spending will rise again in 2027. In the same quarter, Google began delivering TPU systems directly into customers’ data centers. Until then, TPUs could only be rented on Google Cloud.
In other words, the TPU is no longer just “the chip Google uses to build its own models.” Anthropic has already announced a deal to use up to 1 million TPUs. Google is now both a model company and a company that sells chips to rival model companies.
What changed from a cloud perspective
Three points.
First, infrastructure information has become competitive information. OpenAI boasted about “100,000 GPUs,” and Google said nothing. For a company that designs its own chips, “how many we used” reveals chip performance and yield. Frontier model infrastructure is likely to be disclosed less and less from here on. That is why the ability to narrow the range from public material matters.
Second, training chips and inference chips have split. In the eighth generation, Google cut the chip in two. Training happens once and big; inference happens endlessly every day. Features like 1 million output tokens only become products when the inference infrastructure can carry them. When choosing GPU instances, it now pays to ask “is this for training or for serving?” first.
Third, part of performance engineering has started to be automated. The 300 TiB case is symbolic: the model has begun reading profiling data and fixing things at scale. For anyone studying this area, the value of judging what to measure and what to verify is only going to grow.
If you want to know what thousands of GPUs end up waiting on, see our summary of the OSDI paper on the three bottlenecks of LLM training. If you are curious about the jobs that actually run this kind of infrastructure, see our analysis of data center job postings at three AI companies.
⚠️ This post separates its sources into three kinds. Facts about Argon (output limit, pricing, internal use cases) come from Google’s official announcement (September 30, 2026) and DeepMind’s evaluation document. Chip specifications are the figures Google published when announcing Ironwood (April and November 2025) and TPU 8t/8i (April 22, 2026); generations are quoted at different precisions (FP8 vs. FP4) and cannot be compared directly. Capital spending figures are based on reporting on Alphabet’s Q2 2026 results. Google has not disclosed which TPU generation Argon is trained or served on, and the relevant parts of this post are inferences based on public timelines. The cost comparison with Astra comes from press reports citing Artificial Analysis.
Frequently asked questions
Was Gemini 4 Argon trained on GPUs or TPUs?
Google has not disclosed Argon’s training hardware. However, earlier Gemini model cards explicitly state that they were “trained on Google’s TPUs using JAX and Pathways,” and Google has never announced training a frontier model on GPUs. TPUs are very likely, but the exact generation and scale have not been officially confirmed.
What is the difference between a TPU and a GPU?
Both are chips that speed up AI computation. The GPU began as a graphics chip, became a general-purpose one used for AI, and Nvidia sells it to anyone. The TPU was designed by Google from the start purely for AI computation, and Google also builds the network that ties the chips together and the software. That makes TPUs good at binding thousands of chips into one, but they have been relatively awkward to use outside Google’s ecosystem (JAX, Google Cloud). The eighth generation adds a preview feature for running PyTorch on TPUs as-is.
Why is 1 million output tokens hard?
An AI writes one token at a time, and each time it must refer back to everything written so far. Those intermediate results used for reference (the KV cache) keep growing as the output gets longer, so chip memory runs short and reading memory becomes the bottleneck. Long outputs therefore need more than a good model: they need inference infrastructure with large memory and fast chip-to-chip communication.
Why split TPU into 8t and 8i?
Because training and inference now want different things. Training runs enormous computations together for a long time, so raw compute and large-scale interconnect matter. Inference — especially for agent-style models that think through long chains of reasoning — cares more about memory capacity, memory speed and latency than compute. Rather than build one chip that does both well, Google chose to build a separate chip for each.
What does it mean that Argon saved 300 TiB of data center memory?
Google has data recording where programs use memory across all its data centers. According to Google, Argon agents analyzed that data, found waste and applied the fixes themselves. In 128 GB servers, that is roughly 2,400 servers’ worth of memory gained without buying hardware. It is significant because a model has started doing, at scale, work that performance engineers used to do. Note that this is Google’s own claim and not a figure that can be verified externally.
Should our company use TPUs in the cloud?
It depends. If you run large-scale training or high-volume inference on Google Cloud, TPUs are worth evaluating on cost. If you have a lot of PyTorch-based code and need to move between clouds, GPUs are still more convenient. What is certain is that the options are widening: Google has started delivering TPUs directly into customer data centers, and rival model companies such as Anthropic are using TPUs at scale.

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